The present application relates generally to methods for forming semiconductor device structures, and more specifically to vertical transistor devices and their methods of manufacture.
Field effect transistors (FETs) are typically formed on semiconductor substrates and include a channel region disposed between source and drain regions, and a gate configured to electrically connect the source and drain regions through the channel region. Structures where the channel region is parallel to the main surface of the substrate are referred to as planar FET structures, while structures where the channel region is perpendicular to the main surface of the substrate are referred to as vertical FETS (WETS). Thus, in a VFET device the direction of the current flow between the source and drain regions is normal to the main surface of the substrate.
A typical VFET device includes a vertical fin or nanowire that extends upward from the substrate. The fin or nanowire forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin or nanowire sidewalls.
Scaling or otherwise decreasing the dimensions of field effect transistor elements includes decreasing the contacted gate pitch (CPP). Pitch refers to the distance between equivalent points in neighboring features. In a planar FET, the minimal CPP is the sum of gate length, contact width, and twice the thickness of a dielectric spacer. In such devices, the gate length may become the limiting factor for further CPP scaling.
In a vertical FET architecture, the contacted gate pitch may be decoupled from the gate length. However, in a vertical FET the contact to the bottom source/drain (S/D) is formed from the top of the structure such that the bottom S/D contact overlaps the gate. This overlapping configuration creates an undesired parasitic capacitance between adjacent conductive elements.
In view of the foregoing, there is a need for vertical FET architectures and related methods of manufacture that obviate such parasitic capacitance and which are scalable to advanced nodes.